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ACCESBUS.PRS
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1993-12-20
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êìôæÄâöéôêÄì ôÄ ÇééäÆÆ.üöÆ ╬╠╬╠╧╧╬╠╬╠╡
α Γ Γ Σ ≥ ≥ . ß ⌠ ≥ │ Simulation, Virtual Reality,
│ Multiple-Player/Single PC Games,
÷τα≤ Φ≥ αΓΓΣ≥≥.ß⌠≥? │ Education and many, many more can
│ now take advantage of ACCESS.bus,
ACCESS.bus is a new open │ the technology that puts Plug and
industry standard for computer │ Play on every PC.
peripheral connectivity. │
ACCESS.bus is a serial │ The ACCESS.bus offers
protocol that uses simple, low- │ advantages to end-users and
cost I2C technology to link │ developers of systems and
multiple devices to a single PC │ peripherals. Multiple devices
port. Peripheral devices such as │ connect to the host computer with
keyboards or keypads, locators │ only one port. Common communi-
(Mice, Trackballs, Joysticks), │ cation methods for a number of
printers, VR gloves, digitizers, │ device types lead to simplified
sensors, actuators or data │ hardware and software
transmitters and others can be │ development. As an open standard
easily daisy chained to the host │ , ACCESS.bus enables cross-
PC. Applications such as │ plat form use of the same device.
CAD/CAM, Data Acquisition, │
αΓΓΣ≥≥.ß⌠≥ ≤ΣΓτφεδεµΦΓαδ │ Standard low-cost I2C micro-
πΣ≥Γ±Φ∩≤Φεφ: │ controllers handle bit-level
│ handshaking, including automatic
ACCESS.bus technology is an │ arbitration and clock
open specification, enabling │ synchronization.
anyone to implement it on host │
systems or in peripheral devices │ αΓΓΣ≥≥.ß⌠≥ ≥εσ≤÷α±Σ ∩±ε≤εΓεδ≥
without fee or royalty. │
ACCESS.bus has a bus topology │ The ACCESS.bus communication
architecture. That is, a single │ protocol is composed of three
host can accommodate up to 125 │ levels: I2C Protocol, Base
peripheral devices. ACCESS.bus │ Protocol, and Application
data rate is 100 Kbits/sec. │ Protocol.
│
αΓΓΣ≥≥.ß⌠≥ ∩τ√≥ΦΓαδ δα√Σ± │ Φ£Γ ∩±ε≤εΓεδ: This simple and
│ efficient protocol defines
ACCESS.bus is a serial bus │ arbitration among contending
architecture, based on I2C │ masters without losing data. I2C
hardware protocol, with one data │ provides for cooperative
line and one clock line. │ synchronization of bus partners
with different clock rates. Bus │ addresses, without the need for
transactions include addressing, │ setting jumpers or switches. Hot
framing of bits into bytes, and │ plugging is the ability to attach
byte acknowledgment by the │ and detach devices while the
receiver. │ system is running, without
│ rebooting.
ßα≥Σ ∩±ε≤εΓεδ: Establishes the │
asymmetrical interconnect between │ α∩∩δΦΓα≤Φεφ ∩±ε≤εΓεδ: This is the
a host computer and multiple │ highest level of the ACCESS.bus
peripherals. The host becomes │ protocol which defines message
the ACCESS.bus manager. The Base │ semantics specific to particular
Protocol defines the format of an │ types of devices. Each type
ACCESS.bus message envelope, │ requires a different Application
which is an I2C bus transaction │ Protocol. Three broad device
with additional semantics, │ types have been identified:
including checksum. │ keyboards, locators, and text
Unique features of the Base │ devices.
Protocol are auto-addressing and │
hot plugging. Auto-addressing │ αΓΓΣ≥≥.ß⌠≥ ≥⌠∩∩ε±≤ εφ ≤τΣ ∩Γ
assigns devices with unique bus │
All three levels of the │
ACCESS.bus protocol are supported │
on the PC. An add-on card │
implements the physical layer and │
uses the base protocol to │
communicate with physical │
ACCESS.bus devices. │
An ACCESS.bus Manager - TSR │
under DOS and a DLL under Windows │
3.1 - controls the operation of │
the physical layer and interacts │
with the ACCESS.bus device │
drivers.Drivers are available for │
multiple ACCESS.bus keyboards, │
locators and printers for DOS and │
Windows 3.1. Also available are │
C language source code examples │
of the interface from │
applications to the device │
drivers ñ │